Ethernet Controller Chip Design Technology

The design of Ethernet controller chip based on IEEE802.3 is mainly described in this dissertation.In this thesis, the background of this project, the protocol of Ethernet (IEEE802.3) , arithmetic for CRC, CSMA/CD and HASH are introduced firstly. The master plan, including the architecture of the system, the module dividing, the design method and the coding style is expatiated scondly. Finally, the detail of each module is explained.Solutions to the key functional modules of the chip are given, such as receiveModule, transmitModule, registers, Fifo, dmaModule, PnPModule and ISAModule. The most important process in chip designing is how to define each module and how to coordinate and interconnect these modules. According to the TOP-DOWN method, interconnection of each module and the interface signals are also defined to communicate between each other, while the internal timing of the module is controlled by finite state machine (FSM). In the down level of the design, Verilog hardware description language is used to describe the circuits. The layout of the Ethernet controller chip is present in the end of this thesis.In conclusion, the final goal of this project is to successfully scheme out an Ethernet controller chip.