Current Characteristics Of The Power Ldmos Devices .0.18 ¦Ìm Cmos Technology

The market of high-voltage products has undergone an increasing growth in the recent years.The high-voltage products are taking more and more portion in the integrated circuit products,and their influence and attraction are becoming more and more significant.The normal working voltage of high-voltage device is larger than 8 V,while that of low-voltage device is no more than 5 V.Since the structure of high-voltage device is not same with that of low-voltage device,the performance of high-voltage device is also different with that of low-voltage device.RESURF structure on an epitaxial wafer is usually used in high-voltage devices,the epitaxial wafer is of high cost.For the power MOS devices,not only a high breakdown voltage has to be sustained,but also a high Ion and I_dsat is required.Therefore,the on-resistance(R_dson) must be lower.As a result,the process conditions must be optimized to improve the tradeoff between the breakdown voltage and on-resistance.The power MOS device studied in this article is power LDMOS(Lateral Double-diffused MOS) device.Power LDNMOS is built on the structure of NGRD (N-Type Graded Drain) with STI close to the drain in it,this is a N drift region between the drain and the channel actually;Power LDPMOS is built on the structure of PGRD(P-Type Graded Drain) with STI close to the drain in it,this is a P drift region between the drain and the channel in fact.This structure can reduce the electric field under the gate and the on-resistance(R_dson) effectively,so that the breakdown voltage can be improved,as well as higher Ion and I_dsat can be obtained.This article presents the study of power LDMOS devices constructed on Ar annealed P Type 8-12Ω·cm wafer,which is low cost and widely used in Ultra-deep sub micron technologies.The power LDMOS dcvices studied in this article is integrated into 0.18μm CMOS technology together with 1.8V low-voltage and 5.0V medium-voltage devices.Power LDMOS,medium-voltage and low-voltage devices are manufactured on the same substrate,utilizing triple well technology. Three kinds of devices are located in three different wells respectively.In comparison with symmetry power LDMOS,asymmetry power LDMOS is more popular because of its advantages of smaller size,higher integration,bigger working current and higher speed.The influences of channel length,drift region doping concentration and high-voltage P/N well co ncentration on Ion and I_dsat are analyzed.More short channel length is,more high drift region doping concentration is, and more low high-voltage P/N well concentration is,more high Ion and I_dsat can be obtained.Finally,the optimized process conditions are found out,under which the best Ion and I_dsat can be obtained with breakdown voltage requirement.This can help to achieve good device performance under low production cost.