Circuit Model For Gste Extract

IC industry has become a sunrise industry of the national economy annually. It produce several hundred billion dollars in the global value of production. A block from the world's first integrated circuit chip, since its inception, the area of integrated circuit chips getting smaller and smaller. Integrated circuits has per unit area of increasing number of components, and now a chip has been integrated with hundreds of millions of gates. With the increased integration into the circuit, it was discovered that constrained the development of an important factor in IC chip design and chip manufacturing is a serious disconnect. Hinder the development of chip design is an important factor in how to verify the correctness of chip design. Traditional analog chip design verification has been difficult to meet the requirements of the formal verification method is based on its rigorous mathematical methods to ensure the correctness of chip design, so the field of chip design has been more and more attention. To achieve the formation of formal verification of the theory and tools related to validation is a key point is the circuit model extraction and simulation.In this paper, first of all research and study of the formal verification of the relevant theoretical knowledge, including the theory of the main branch of development. And is currently the mainstream of the field of formal verification algorithms GSTE conducted in-depth study and research, and compared the algorithm with the traditional algorithms different.Second, pairs of digital circuits and digital circuit design method related to a summary study of digital circuit design front-end circuit description and digital circuits formal verification algorithm point. Analysis of how the circuit model expressed in the computer memory, data structure, and studied how to use language to describe a circuit extraction algorithm suitable for use GSTE to verify the circuit model, allowing GSTE algorithm can be applied to practical circuit design zoneThirdly, in the current academic and industrial circles some common tools SMV, VIS, FORTE and other research and source analysis, and the current circuit design language VERILOG learning studies, in view of the above tools offered by the circuit description language summarized on the basis of grammatical simplification VERILOG produced a set of algorithms for verification tools GSTE circuit description language syntax and semantics, so that it could easily describe the circuit and the circuit model extraction. Using the compilation tools LEX, YACC implements the circuit of this software enter the front end, in the syntax tree generated from semantic reasoning, the circuit model of the data structure binary decision diagram by the back-end authentication algorithm GSTE Formal Verification of the circuit model. In order to visual observations of the circuit description language describes the circuit behavior, this paper in the digital circuit simulation carried out relevant studies, based on the extraction of the circuit model, realization of the circuit model of the simulation, the corresponding waveforms can be, never be able to convenient presentation of the GSTE algorithm.Finally, the paper conducted a systematic and comprehensive summary of conclusion and pointed out the lack of design tools in this article, as well as the next step to improve the direction and looks forward to the formal verification algorithm in the field of circuit design a good application prospects.