Aes Encryption And Decryption Algorithm Of High-speed Asic Design

Today, with the developing of information technology, many new types of communication and information storage continue to emerge, such as: 3G mobile communication technology, physical networking (wireless sensor networks), mobile storage, cloud computing technologies, and so on. The exchange of information increase the amount of non-linear reality and put forward a higher level of information security requirements. encryption standard DES, which has been widely used are increasingly In the past, is appearing to be inadequate. so AES encryption Standards with higher efficiency and safety become more important.Firstly, this paper describes the status of information security and encryption technology, and analyzes the AES standard encryption and decryption process and the various steps of the basic transformation.Secondly, this paper describes the use of encryption and decryption algorithms multiplexing, and the external and internal pipelines to achieve a high-speed design architecture. For the module of SubBytes in this article, there is no way of using look-up table design, instead of using the AES algorithm is the inventor of the proposed an alternative method: using finite field inverse operation and affine transformation by way of design. We cite an equivalent decryption algorithm for processes in the re-use design, so that decryption process consistent with the order of encryption processes. Improving the re-design of such extent, while also simplifying the original key schedule round the table to do a MixColumns transformation, the results become the key scheduling table in this equivalent decryption process. In the pipeline design, use round of the external line will require 10 times the original iteration of the round of encryption start, so that system can have data to output during each clock periods. We, using internal pipeline to divide encryption rounds into several delay paths, improve clock frequency. Since the SubBytes operation of the system being achieved by using the finite domain transform, so the system delays are mainly located in SubBytes module. There are four pipelines in this design. ShiftRows transformation, MixColumns transformation and AddRoundKey operation are assigned in a pipeline interval, and the SubBytes operation is assigned in other 3-stage pipeline segmentation. This round of the combination of internal and external pipeline is designed to provide the same circuit structure of the encryption and decryption process, the speed increased by 30 times.Thirdly, the design of the main steps in accordance with the design process, namely the use of modelsim, synopsys DC, SoC encounter, carlibre tools such as simulation of the system work, and system as a back-end processing.Finally, the summary and analysis of the papers mentioned in the work; analyze the inadequacies of the paper and to discuss how to improve it and discuss the next stage of work.