Research On FFT Acquisition For A GPS Receiver And Its FPGA Implementation

GPS receiver has been widely used in both military and civil areas for its significant functions such as positioning and navigation. Signal acquisition is the first step processing inside the receiver, so as to determine which satellites are visible in the sky. The difficulties during designing lie in how to realize acquisition as quickly as possible under high-dynamic environment. The hardware design through FPGA (Field-Programmable Gate Array) can has a great advantage in this area, for its efficient performance, its highly integrated characteristic and its capability for circuit design and even system circuit design. As such this thesis is focused on the study of FFT acquisition circuit design under high-dynamic environment based on FPGA.This thesis describes the acquisition module's working principal inside a GPS receiver, compares merits and drawbacks of the serial linear searching method and the parallel code-phase searching method via FFT. Since the former method's speed is slow, and can only applied in static or time-loose circumstances, whereas the latter is fast and efficient and reliable, this thesis implements a design using the latter method under QuartusⅡdeveloping environment through verilog HDL (Hardware Description Language). Total design mainly consists of six modules, which are FFT/IFFT Transform module, local carrier generator module, local pseudo-code generator, averaging down-sampling module, value-calculate and judging module. To test and verify the design, this thesis uses real GPS data to carry out functional simulations and timing simulations. Simulation results indicate that the designs are correct and the performance is reliable.In addition, to realize reliable communications between receiver and peripherals, this thesis designs a UART interface beside the acquisition circuits, the bond rate is 512Kbps, including both sending and receiving functions. Simulation results show that the design is correct.