Full Custom CAM Design Using New Cell And Match Line

The tag of the TLB (Translation Look-Aside Buffer) which is on the critical path of Microprocessor Core contains Data Array and Tag Array. The Data Array is generally implemented by SRAM (Static Random Access Memory), and the Tag Array is generally implemented by CAM (Content-Addressable Memory). As the key path, the CAM enables TLB to speed up the mapping from virtual address to real address rapidly with parallel match.So the speed of CAM impacts the microprocessor greatly.CAM designed by full-custom design has advantages such as faster speed and smaller size, therefore has important practical value and theory signification. On the basis of deeply study on the full-custom CAM technology, in 65nm CMOS this thesis designed CAM which meets the requirements of TLB by optimizing the circuit and layout of CAM besides, as well as comparing different CAM Cell. After that, we proposed the new rapid circuit structure of match-line.Main contribution and innovative points of this thesis are given as follows:1,Designed and completed two CAM Cells: 8 MOS transistor CAM Cell and 12 MOS transistor CAM Cell. The former has advantages of simple logic and small size, while the latter has strong advantage on the speed.8T CAM Cell has excellent performance in speed,squre,stability and so on.So it is used as a part of CAM designed in this thesis.2,Optimization and improve of a new match-line structure:Inverter control hierarchical match-line structure. The line is divided into high digit and low digit by using "1" match and "0" match of the CAM Cell, and this structure can fastly pull down local match line than traditional structure, thereby it displays better matching performance through highear discharge and low charge compensation method.3,Full-custom implementation of the CAM in the TLB. The match operation,address decoding,read and write operation are operated in the pos-edge of CLK, while local match-lines and pre-charge of global match-lines are operated in the negative edge of CLK. layout simulation show that the operating frequency is 2GHz, The delay of read operation is 396ps, the delay of write operation is 386ps and the delay of match operation is 409ps ,total area 0.0832mm2 at the common cases.