Modeling Of Signal Transmitting On Chip

This paper purposed models for two types of block, ALU block and storage block, and experiments about accuracy and quality to design circuits'details of block. For ALU blocks, model oflogical signal transmitting using key data extract from HSPICE experiments based on industrial MOSFET library, and could get delay parameter matrix which could calculate nets voltage wave and get delay character for static timing analysis, and can be reference of how to optimize details of logical circuits. Taken mirror adder carrier chain as example of calculation, it could get results of key RC delay time from MATLAB and HSPICE that are both about 10ps. Comparing with half-custom delay library, this model concludes information of load of next stage. For storage array, a model of transmission line based on Laplace transform is presented, this model could be calculated repeatedly used by second or more-order frequency function, in which a signal of voltage difference between stimulus and response is proposed. It is possible to calculate high iterative discrete convolution with computer instead of analytic continuous convolution, because the mentioned voltage signal reach to zero when the time variation reach to infinity. The model could be used in analysis of delay specificity in large-scale storage array. The model is more approaching to physical analysis and HSPICE simulation results than traditional Elmore model, and comparing with HSPICE results, the accuracy is about 67.8%~98.1% during different voltage swing and RCtime.