Low Redundancy Adjacent Double Errors Correction Codes In Memory

As the integrated circuit technology develops to the deep sub-micron field, memory storage node is more susceptible to the influence of space radiation particles, causing the data in memory upset more easily. Memory unit size decreased makes one die can be placed more memory units, so the distance between the memory units decreased and the SEUs causes multiple bit upsets more likely.Due to the nature of high-energy radiation particles, the probability adjacent double bit errors is much higher than other multiple bit errors.This paper focus on how to realize the SEC-DED-DAEC ( single-error-correcting, double-error-detecting, double adjacent-error-correcting)code using the least cost.Through discussing the mathematical theory of linear block codes, we can get the conclusion that the correction capability of linear block code is due to its parity-check matrix.The certain mathematical theory and the improvement of procedure are utilized to narrow the searching space of the parity-check matrix and find the parity-check matrix which fits the conditions of the proposed code and reduces the probability of the miscorrection of non-adjacent double error. Based on the bits of information for 16, 32-bit and 64-bit words in memory, the paper find the parity-check matrix which can satisfy the SEC - DAEC correct code requirements.According to the parity-check matrix with hardware description language, 16, 32-bit and 64-bit bytes of memory error correction circuit designs are completed .Combined with static storage verilog memory of an SRAM behavior model, using the method of fault infuse error; the function of the correction circuit is validated. The proposed code which based on linear block codes has the same number of check bits and nearly the same cost as the conventional SEC-DED code that can only correct 1-bit error. The proposed code can detect 2-bits errors and correct adjacent double errors, thus improving the reliability of memory.