Design Of UHF RFID Tag Chip Baseband Based On Independent Standard

Radio Frequency Identification (RFID) is a kind of technology that uses space coupling of radio frequency signals to achieve non-contact information transmission. In recent years, RFID has been widely used in the worldwide, such as transportation management, military management, and so on, thus it is becoming a hot topic of research. Electronic tag, which operates in accordance with the air interface protocol, is one of the core components of RFID system. But currently, all the electronic tags are designed based on foreign standards, which will bring great security risks to our country, and produce a large number of patent fees, so it is of great significance that we design electronic tag chip based on independent standard.In the beginning of the paper, the research background of RFID technology was introduced. After that, the development of RFID-related standards was focused, then we discussed the current situation of tag chip design in China and the world.Following the above content, the national military standard: "Air interface for military radio frequency identification Part 1:800/900 MHz parameters", with our own intellectual property rights, was introduced, and the key technologies involved were discussed and analyzed in detail. On this basis, we divided the digital baseband of electronic tag chip into several modules, and designed each module separately in the RTL-level, which was prototypically verified by FPGA hardware platform. In the RTL-level design, a novel scheme of reducing power consumption was presented, through reasonable module partition, adopting power management unit, multi-clock-domain, pipelining, clock gating, and so on, the power consumption of electronic tag chip was decreased greatly.Furthermore, after verifying of the RTL-level design, we translated the RTL-level codes into gate-level netlists through logic synthesis, and discussed the methods of configuring clock paremeters while synthesizing, then we analyzed and verified the results of synthesis. After verifying of the netlists, we started to the physical design of electronic tag chip, the methods and steps were analyzed, and the new netlists were verified through simulation. Finally, we obtained the layout of electronic tag chip, which was taped out with SMIC 0.18μm process. The test results of the electronic tag chip were given at the end of the paper, which indicate that the functions of the tag chip were correct, and the test results were consistent with the simulation results.