Research And Implementation Of The DMA Controller And The Memory System 2D Extension In YHFT-Matrix DSP

Currently, high-performance general-purpose DSPs gradually evolve as multi-core and vector ones. The Memory System will be an important factor that restricts the per-formance. Based on the real-time applications such as Wireless Communication, Video and Image Processing, this paper studies the Vector Memory System in the YHFT-Matrix DSP, which is a high-performance general-purpose DSP independently developed by the National University of Defense Technology. The main work of the paper is as follow.Firstly, according to fearures of the DSP architecture and the main real-time appli-cations, a multi-channel and multi-bus DMA controller is designed to meet the needs of the data storage and access on the chip and support flexible matrix access.Secondly, in the sliding window algorithms of the image and video applications, the original 1D Memory System and DMA controller perform low-efficiency in data storage, access and reuse. To solve this problem, this paper proposes a Memory System with the 2D Extension Scheme. It includes an original Vetor Memory and a novel 256KB 2D Memory supporting both 1D and 2D access. And several corresponding Load/Store Instructions are designed.Finally, to support the 2D Extension Scheme, a dedicated DMA channel is imple-mented to support data transafer between 2D Memory and off-chip memories. Besides, an intra-DMA with 512-bit width is designed between 1D and 2D Memory in order to improve the performance of the Memory System.The proposed multi-channel and multi-bus DMA controller and Memory System with the 2D Extension Scheme are fully verified. At last, this paper evaluates the pro-posed memory system by applying YHFT-Matrix DSP applications and gives the syn-thesis results under TSMC 65nm technology. The experimental results exhibit that: (1) The bandwidth of VM Bus in the DMA can reach up to 15.6Gbps, meeting the band-width and configuration flexibility requirements of the main real-time applications. (2) The 2D memory can obviously accelerate the sliding window algorithms in image and video applications. The speedup of the SAD algorithm and Gauss Filter algorithm can be up to 3.0 and 1.6 respectively. SAD, Gauss Filter and Median Filter save 42.5% of memory access and 52.8% of memory space on average. The synthesis results show that: (1) The DMA controller can operate at 800MHz with the area of 362,480um2 and the power consumption of 20.29mW. (2) The 2D Memory can run at 1GHz with the area of 1,974,306um2, of which the area of the control logic is only about 5.47%, and the pow-er consumption of 103.62mW.