Key Technology Research In Converting 2D To 3D Video For Embedded Application

Recent years, three-dimensional imaging and display technology has developed rapidly. A variety of three-dimensional display devices have emerged in the market and the audiences can experience three-dimensional effect in many ways. However, the source for three-dimensional imaging is scarce for the difficulties of the calibration, complexity of post-processing as well as the high cost of shooting, etc.. Naturally, the technology which turns flat video to three-dimensional video is getting more attention.Currently, the mainstream technology of turning flat video into three-dimensional video has its problems, such as, the algorithm adapts to a narrow scope of applications, and the support to mobile devices is limited. These problems affect the practical applicability of automatic three-dimensional video technology. In response to these shortcomings, this paper designs an automatic depth estimation algorithm based on classification of video content which follows 3 steps. Firstly, by analysis of video motion type, call the method "depth from motion " or " structure from the motion " to get the motion vector; secondly, integrate motion vectors and the results of color based image segmentation to optimize the depth map; finally, use asymmetric bilateral filtering to proceed the post-processing. Compared to the existing technology, besides the maintenance of the effect of the depth, the scene can be handled substantially by this algorithm, and it also enhances the usefulness of automatic technology of converting 2D video to 3D video; secondly, by analyzing three-dimensional imaging principle, this paper designs a depth image based on rendering techniques (DIBR), which is suitable for hardware. Through mathematical optimization, cutting pipeline, designing dedicated cache and other methods, it can significantly improve processing speed and reduce hardware costs. The evaluation results demonstrate that on Xilinx Virtex-5 FPGA platform the proposed arithmetic can achieve 1.8 times improvement at speed and the hardware cost is only 1/30 compared with the previous implementation.