Research On The RTL Components Design Automation

With the process dimension of integrated circuits(IC) steps into deep sub-macron level, the physical parasitic effect which represents by interconnect delay has become a dominant factor in the performance of integrated circuit. It is necessary to integrate the high level synthesis and floorplanning when we design the circuit. It is not suitable to obtain static RTL components directly in this process, the reason is as followings:firstly, the treatment of interconnect delay of static RTL component is difficult to obtain to satisfy the design requirements; secondly, the sharp could not be changed for the ratio of RTL component is fixed. RTL component should be dynamically generated in the integrate process of high level synthesis and floorplanning. In this thesis, a design approach of RTL components automatically was presented, and the design process of RTL components was divided for three stages:simplification of logic function, layout design and parameter extraction.The first, logic function was simplified. A fast and accurate simplificated method based on Q-M method was presented by a new merge rule. The size of implicants set was decreased by a pair of weights in the iteration process of comparison, and all prime implicants could be obtained by the integration of implicants which satisfy the conditions, finally. The minimum coverage of logic function would be obtained by the following process:bipartite graph which consists of prime implications and minterms were constructed. The minimal set of prime implicants implicate all of minterms, that is, the minimum coverage of logic function has been obtained.The second, simulated annealing algorithm (SAA) was employed to obtain the module placement which was needed by the logic function. The area of rectangle which encloses all the modules was used optimization target. The layout was based on slicing tree, and the expression of layout was normalized polish expression (NPE). The appropriate parameters were selected in SAA, and the layout was obtained finally. The relative position of modules was displayed by graphical display program.Finally, RTL component's area and delay were extracted. Slicing tree is traveled in post order, the area of rectangular under every operation node of slicing tree was calculated, and the area of root node was the RTL component's area at last. The interconnection delay between modules was calculated by Elmore formula, delay between input port and output port of RTL component was obtained by traveling all paths from input ports to output ports and the maximal one was selected as RTL component's delay from input port to output port.Three stages of RTL components design automation has been researched in this thesis. Compared with other logic simplification methods, method in this thesis was faster. The utilization of area obtained SAA was higher than the one local search algorithm. Finally, an example of RTL component design was presented, according to the experiment result, the approach presents in this thesis was feasible.