The Low Power Design Based On The State Machine Coding

Moore's Law advances that transistor counts would double every 18 months and the speed of CPU be faster. The power has become the main problem in the IC design, and low power design techniques have became essential for today's VLSI industry. Most of VLSI circuits are sequential circuits. Sequential circuits can be simulated by symbolic Finite State Machine (FSM). So it is important to do some research on the Optimization of Low Power FSM.The work of this paper is to make the low power design based on the existing state machine coding. There are two main experiments to compare the optimizing efficiencies according to the experiments'results on gate switching activity rate. Three main contents are included as follows:To introduce the basic information of the state machine, such as the concept, elements and the varieties of the state machine and their codes.To design two experiments related with the state machine based on the knowledge of the elements of the state machine. The first experiment chooses a simple 4-bit state machine, and the second is on UART transmitting machine. Then, to make the low power analysis using the Verilog-HDL, and then to compare the results.To simulate the codes in this experiment using the Modelsim 6.0 tool. And then to compare their results. So that I could know the conclusions of the experiments. After running the two experiments I can concluded that: using the 2-bit Binary code to design the state machine (corresponding to 4-bit One-hot code, 2-bit Gray code), the power is 33.3% lower than that of the One-hot code. However, the power of the state machine by Gray code is optimizing 33.3% than Binary code. So far in the two designed experiments, the power of Gray code is the lowest, Binary code higher, One-hot code the highest of the three codes.When I designed state machine, I prefered to choose Gray code for its low power trait.