Application And Research Of LVDS In DSP System

In the information age, data transmission system must have a wider data bandwidth and a higher transferring speed. With the development of technology, process dimension is getting smaller, and the supply voltage is becoming lower. But some imperfect factors come out at the same time, skew, crosstalk for example. The common parallel I/O interface circuit,because of its own circuit structure's restrictions,can no longer meet the microprocessors,multimedia and the data bandwidth of network technology requirements.Serial transmission can ensure the reliability of the data transmission,it becomes the primary mode in high-speed transmission system. Signal is often transmitted with low-voltage and low-swing in serial transmission system and the data transmission system can get a higher data rate while both the consumption and cost are very low.Low Voltage Differential Signaling (LVDS) technology can realize the high-speed and low-power data transmission. LVDS is the serial high-speed interface based on low-voltage and low-swing differential transmission technique. It is widely used in many data transmission circuits. This article presents a high performance CMOS LVDS circuit based on high-speed data transmission theory, it can be applied in Digital Signal Processor(DSP). Some innovation and technical difficulties have been solved in this dissertation, and they are summarized as follows::1. A new pre-emphasis circuit is utilized to have a very low total equivalent input capacitance, which can minimize the attenuation of signal when it is through the long cable distance and ensure the reliability of the signal transmission.2. The optimization of common mode feed-back circuit has been made so as to keep the common voltage stable at high operating frequency. The proposed circuit with no resistance occupies smaller area and has better performance.3. A novel receiver circuit is designed which is composed of a pre-amplifier, a CMOS voltage reference, a hysteresis comparator, driver buffer, receipts a wide range of common mode voltage.4. A novel pre-amplifier circuit is proposed, and the driver buffer combines the level shifter circuit and shaping buffer circuit together. This structure has smaller layout area and better performance.5. A Fail-Safe circuit is designed to ensure the safe operation of the whole circuit.This LVDS circuit with 1Gbps data rate is implanted in 0.18μm standard CMOS technology. Simulation results indicate that the LVDS transceiver achieves the design target with the correct function.