Research On Key Techniques Of Multi-standard Video Decoder

The designs are based on the standards of AVS and MPEG2video decoder; they are mainly applied in DTH (Direct to home) project of digital television. The main achievements are as follows:The designs of main modules of video decoder based on AVS and MPEG2is achieved, these designs are simulated by RTL. The architecture designs of whole decoder is adopted double CPU controlling. One Mailbox controller is used to improve the performance of communication between decoder and external devices. The whole VLD is controlled by using state machine, there include a mechanism of error detection which can achieved error detection and Concealment when there are some errors in the stream bits. After the investigation on the two standards' arithmetics of IQ/IS, one based on pixel level multi-pipeline design is proposed to enhance the work frequency and decrease the circuit resource consume, synthesize by Synopsys Design Compiler, the work frequency can reach to161.6MHz, equivalent circuit are about1600, compared with literature32, this design can be used to save55%of resource consume.For decreasing the area consume and improving velocity of the circuit, the IDCT module of MPEG2is adopted a reformative arithmetic which are based on Loeffler, one approximate and intensify of multiplier designs are proposed to reduce miscalculation. The simulation result shows that the miscalculation of IDCT calculated data can be controlled between-0.5and1(the permissible rangs of standard defined are from-2to2).Architecture of multi-stage pipeline based on macroblock-level is designed. For decreasing the needed cycles of fetch referenced datas, one external memory interface module by using an Buffer size of3k is designed to reduce the needed clocks of interpolation calculation, this Buffer can be used to save42percent of decoder's system power consumes. For further reducing needed cycles and improving the performance, one special frame memory structure is proposed:external DDRAM keeped6high definition frame pictures. Because of the motion compensation interpolation calculation are based on field, so, the top field and bottom field of one frame picture are separated stored for decreasing the clock consume of fetching referenced datas, the MC module are synthesized by technology of90nm, the result shows that the work frequency can reach to135MHz, resource consume are about45.48k (not include the DDRAM's consume), the motion compensation interpolation dealt with one macroblock are needed about520clock cycles, this can saved15%clock cycles compared with literature33.One test platform is constructed. The verification included module-level and system-level. The module-level verification is adopted two ways:one is to compare the C software outputting results with RTL simulation; the other is by comparing the results of MATLAB software simulation with RTL. The system-level verification are used one720*576sized video sequence. At the2Mbps bit rates, the PSNR ranges of the outputting frame pictures are from25.8to33.6; the simulation result shows that these designs are satisfied.