Emccd Timing Generator And Its Drive Circuit

The electron multiplier charge-coupled device (EMCCD) with high quantum efficiency, high spatial resolution, good reliability, stable performance, compact structure and so on, can amplify the weak photoelectron signal inside the chip. The EMCCD imaging system, therefore, can realize the target detection and imaging of low level light. In order to better understand the characteristics of EMCCD and master the techniques which will be applied to astronomical low light level imaging, we take an EMCCD component TC285SPD manufactured by TI as an image sensor, and develops an EMCCD imaging system or EMCCD camera.In this dissertation we give a brief introduction of the EMCCD component used in the system, and describe general structure and design requirements of the EMCCD imaging system, then focus on two designs of the driver circuit and the driving timing generator of the EMCCD camera. According to the TC285SPD peripheral driver circuit recommended by TI, we carried out the schematic diagram design and the PSpice simulations. For one of the key technologies of EMCCD cameras——charge multiplication driver circuit, we take several methods to improve and optimize the PCB, such as using4-layer board solution to separate a power layer and a GND from2signal layers, power integrity design skills to reinforce the power source, and isolating magnetism beads and decoupling capcitors for the power sources to improve EMC and the EMI performance of the circuit, as short as possible routes between the driving output pins and the MOSFET gates to enhance on-off performance of the driver. The test results manifest that the driver circuit can operate in frequencies of10to40MHz for input clocks and meet the requirements of the EMCCD charge multiplication, and while the driver test results published by domestic counterparts are obtained in frequencies of not greater than20MHz. According to the multiplex driving clocks in the EMCCD camera and their control requirements, combining the VHDL programming with the NIOS soft-core design, we carry out the programming of the timing generator with two driving modes, one for frame transfer clearing and another for frame transfer readout. Functional simulations prove that the genrator can control accurately the EMCCD driving clocks, the ADC control signals and Camera Link transmission signal. Thus using the generator based on FPGA, it is possible to reduce the dependence on its periphery hardware circuit, and make the whole design more concise and easy to debug. Finally, according to the control requirments of the imaging system, we set up a embedded test bench based Altera SOPC, and carried out several tests for the driving timing control software and hardware. The final test results are given. After analysis of the test waveforms, we think that the timing of the EMCCD clocks from the designed generator can meet the requirements of the imaging system.