Research And FPGA Implementation For Receiving Algorithm Of Weak Satellite Navigation Signal

Indisputably, satellite navigation system has already proven its success in wide application in alltrades and professions. However, with wider application, in the indoor, forest, tunnels, and so on, thesignal will be attenuated heavily. Because indoor signal strength is low10-30dB than outdoor signal,the usual receiver is difficult to meet the environmental requirements. Therefore, research onreceiving weak satellite navigation signal has become a hot spot. The thesis mainly explores toimprove acquisition and tracking performance of navigation satellite weak signal. The main contentsare as follows:1) The acquisition princible is elaborated. Serial search acquisition, parallel frequency searchacquisition and parallel code phase search acquisition are analyzed and compared. Analysis showsthat increasing the coherent integration time and non-coherent integration time can improve SNR.However, coherent integration gain is limited by navigation message and frequency offset. And,non-coherent integration will bring square loss. By implementing rigorous mathematical analysis, thisthesis proves that differential combining outperforms (DFC) conventional non-coherent integration(NCH) in the detection of weak GPS signals. The processing loss induced by NCH can be decreasedthrough the use of DFC. The form of DFC which is easy to be implemented on FPGA/DSP isdesigned. At the same time, the causes and mitigation technique of cross correlation is researched.2) According to the mathematical model of the loop, performance and tracking measurementerrors in weak signal environment are analyzed. Two-order FLL-aided three-order PLL for carriertracking loop and carrier-aided two-order DLL code tracking loop is designed and implemented.3) Acquisition with large parallel correlator is designed and implemented on FPGA, includingthe module of carrier NCO, down-conversion of phase rotation, code NCO, PN code generator andrelation-coherent integration accumulators. The results of relation-coherent integration accumulatorsare transfered into DSP to implement DFC and tracking loop. For testing the receiving performance,the multi-channel GPS signal simulator implemention model is analyzed, and C/A code signalsimulator of GPS satellite is implemented on FPGA.Through the test, the design is verified to befeasibility.