Research On Electrical Characteristics Of Nc-Si Floating Gate MOS Structure And NOR Flash Memory Arrays

With development of microelectronics, the feature size of semiconductor device becomes smaller and smaller. As the thickness of tunneling oxide of traditional nonvolatile floating gate memory turning into nano-scale, the consequent aggressive scaling of the memory technology is destined to face serious limitations in the next years. The limitations are mainly due to lateral leakage current and quantum tunneling effect of scaling the dielectrics without losing data retention or degrading reliability. Silicon nanocrystal memories, in which the continuous floating gate of the conventional FLASH cell is replaced by an ensemble of nanocrystalline islands, are promising candidate to overcome the above mentioned limitations and to continue the scaling of FLASH devices.In this paper, we fabricated the nc-Si floating MOS structures by deposition in system of plasma-enhanced chemical vapor deposition (PECVD) following with annealing process. Capacitance-voltage and conductance-voltage measurements are adopted to investigate the electric characteristics. After obtaining nc-Si floating gate MOSFET successfully, the memory matrix of NOR frame is designed and intrablock disturbs are discussed in details. At last, the realization of NOR function driven by the peripheral circuit is elucidated.In order to obtain high quality nc-Si floating gate MOS structure, we fabricate the samples with two steps:1) depositing a-Si floating gate MOS structure in PECVD system;2) annealing in the nitrogen ambient for partial crystallization under the constrained crystallization principle. In the cross-section high resolution TEM photos, we observed the size and lattice fringe of separated nc-Si dots. By Raman scattering, we verified the coexistence of nc-Si and a-Si due to the crystallization of a-Si. The average size of nc-Si dots and crystalline ratio is also confirmed by Raman spectra.Capacitance-voltage measurements are carried out to investigate the storage characteristic of nc-Si floating gate structure. The size effect of nc-Si is researched to find that as the nano-dots become larger, the memory window becomes larger and threshold voltage turns smaller. G-V measurements are carried out to get the details about carriers injecting into nc-Si or interface traps. The G-V peak characteristics with frequencies due to nanocrystals are identified to be different from that of the interface traps. Double-layer nc-Si floating gate MOS structure is prepared and the improvement of memory window and retention time is discovered compared to that of single-layer nc-Si floating gate MOS structure,.We also found some interesting phenomena appear in our C-V measurements. First, capacitance in the inversion area decreases which is caused by deep depletion. Second, C-V curve in the inversion area goes which is attributed to positive charge’s lateral spread on the electrode. Third, the clockwise C-V hysteresis window of nc-Si floating gate MOS structure is investigated and this is induced by the injection of carriers from electrode into traps in the SiNx control layer. Finally, the interface state caused the irregular change of C-V curve in the depletion. After discussion, we proposed some corresponding solutions to solve the problems.MOSFET with nc-Si floating gate were fabricated successfully on production line of0.13um in SMIC. The electrical characteristics of memory cell show a good performance. Based on this we mainly discuss the design of NOR flash consisting of nc-Si floating gate MOSFET array. The intrablock disturbs meaning that an intentional operation on a given cell disturbs charge stored in neighboring cells were well discussed. The operating voltages of reading, programming, erasing were designed. Further, we considered the peripheral circuit of NOR type flash cell array and investigate the working principle of NOR type memory array under controlling of peripheral circuit.