The Research And Design Of A High Efficiency DC-DC Converter In0.5μm CNOS Technology

In the modern industrial field, highly sophisticated electronic system has laid afoundation for the future technical breakthroughs in the information industry, such asthe application of multiprocessor unit and system on chip. However, the fast growthof the system’s complexity and functions means more power consumption. Thisseriously limits the miniaturization of the system, it also affects the system’sefficiency, reliability and service life. Power management technology is introduced inorder to slow down this critical power crisis. Switching power supply is considered tobe the best choice, because of its high efficiency and flexibility of voltage conversion.This paper mainly expounds the design method of the boost converter, anddifferent kinds of control method of the boost converter, give a detail explanationabout the typical control methods at the same time. Based on the analysis of the maincircuits of boost converter, this paper applied the lyapunov theory to control modelingsimulation, verified the switching power supply technology in theory. Then did thedesign and simulation work about the sub-circuit of the pulse width modulationsynchronous rectification boost converter, including the error amplifier、bandgap、synchronous rectification circuit、 current sense circuit, clocking circuit, slopecompensation and soft-start circuit. On this basis, simulated the whole circuit, thenanalyzed the important parameters through the simulation results and the calculation.The designed high efficiency boost DC-DC converter using pulse widthmodulation current control mode and the synchronous rectification technology, itworks in inductor current continuous mode. The working frequency of this converteris1MHz, fixed output voltage is5V, achieving the highest efficiency is95.4%whenthe load current is100mA. The whole circuit layout drawing was finished by a certainmanufacturer0.5μm CMOS process, and the overall layout of the chip was checkedby regular verification-Design Rule Checking verification and Layout VersusSchematic verification, the chip layout area is1225x1620μm2. Finally, according tothe layout extracts parasitic parameters, we did the netlist simulation, and compared the pre and post simulation results.The simulation results show that the DC-DC converter with good linearregulation and load regulation, its also has a safe start-up process at the same time.This further verified the rationality and accuracy of the suggested high efficiencysynchronous rectifying DC-DC converter.