Research And Design Of Switched-capacitor Amplifier Used In Pipelined ADC

At present, the switched-capacitor amplifier is becoming an integralpart of mixed-signal processing circuit within40years of development. Inorder to be processed in the digital domain, external analog signal must betransformed into digital signal by the analog to digital converter (ADC).The switched capacitor amplifier which can achieve the function of thesampling, filtering and quantizing is undoubtedly the core of the ADC.However, the advancement in CMOS technology and dropping in powersupply have brought new challenges to the switched-capacitor technologyand designing of the operational amplifier. How to design low-voltage high-speed high-precision switched-capacitor amplifier has become a new hotspot in designing ADC. Based on SMIC0.13um CMOS process and with a1.2V power supply, a switched-capacitor amplifier is researched anddesigned which could be used as a sample-and-hold circuit in a14bit,100MHz pipelined ADC.Firstly, this thesis introduces the research background of the switched-capacitor amplifier and basic applications, and then the non-ideality factorsof the switched-capacitor amplifier and the resulting errors are analyzedcarefully. Based on the theoretical analysis, a sample/hold circuit isdesigned: Considering the limit in input and output swing by voltagedropping, and reducing op-amp design more difficult, the overallarchitecture employs the charge transfer structure; according to therequirements on noise by the performance of the circuit, and the practicalengineering design considerations, sample capacitor is determined; a two-phase non-overlapping clock circuit is designed to achieve precise control;the bootstrap switch is designed, which can be better applied to the lowpressure environment to reduce the nonlinear error. Focused on thedesigning of a two-stage folding cascode op-amp, the auxiliary op-amp isreasonably set to achieve high gain and guarantee the stability of theoverall op-amp. To stabilize common mode output of differential operation amplifier, two discrete time common-mode feedback circuits are designed,respectively.Finally, based on SMIC0.13mixed signal1.2V CMOS technology, eachmodule circuit and the overall circuit are simulated and analyzed inCadence Spectre. The results show that the op-amp loop gain is109.7dB,loop unity gain bandwidth is673MHz, phase margin is78°, which meetthe design specifications. With sample frequency100MHz, common modevoltage0.7V and differential input0.5V, the output has been established tobeing within0.01%accuracy in3.465ns, stabled in the accuracy range as(499.97mV,500.03mV). With a sine signal with0.5V amplitude and48.68MHz frequency being inputed and analyzed by FFT, the samplingpoints are2048, the spurious-free dynamic range (SFDR) is91.6351dB,effective bits is14.265bit, which could meet the requirements of S/Hcircuit in14bit100MS/s pipelined ADC.