Study On Retina-Mode Readout Integrated Circuit For IRFPA

Infrared focal plane array (IRFPA) has been widely used in field of the nationaldefense and also has a vast market prospects in the industrial and civilian fields. Forexample, it can be applied to precision-guided, nighttime combat, searching andtracking, visual enhancement etc. Readout integrated circuit (ROIC) which has thefunction of receiving infrared detector weak signal, amplifying, background suppression,noise reduction, and readout is an important component of IRFPA. So the performanceof ROIC has a great effect on IRFPA system. With the expanding of array size, thebottleneck between IRFPA output and the follow-up image processing system becomemore and more serious. Coupled with the high background and low contrast features ofthe IR signal, it put forward higher requirement on the accuracy and speed of thefollow-up ADC. This obviously increases the follow-up image processing system’scomplexity and difficulty. Therefore, some signal processing functions are desired to beintegrated on-chip to solve that bottleneck problem. This kind of ROIC is called“Readout and Processing Integrating Circuit (ROPIC)”.This project is supported by NSFC (No.60702007). Based on analysis of thepresent status of ROIC at home and abroad, the silicon retina and some relatedneuromorphic circuit model has been studied in this paper. Borrowing thoughts from thesilicon retina, the function of edge detection on-chip is achieved by integrating thesignal processing functions of retina on the traditional CMI readout structure. The pixelunit consists of background suppression circuit, current amplification circuit, CMI(current mirroring integration) unit,2D filter network and current mirror subtractioncircuit etc. The integration unit, CDS (Correlated Double Sampling) unit and S/H(sample&hold) unit were shared by column and the serial rolling readout mode wasadopted. This proposed ROIC was sensitive to abrupt signal of image edge andnon-sensitive to smooth signal. The local adaptation was achieved, benefited from thisfeature of edge detection. The Spectre simulations of1×20linear array and20×20areaarray were implemented respectively based on CSMC0.5um2PTM standard CMOSprocess and the layout of10×10array is designed。The on-chip driving circuit for ROICis designed by using Verilog HDL, the logic synthesis tool Design Compiler and theauto placement and routing tool Encounter SOC,in order to improve the integrationlevel of IRFPA and satisfies the requirement of diversification readout.