On-chip Interconnection Building Block Optimization

MPSoC (Multi-Processor System-on-Chip) has become the main choice of high performance embedded system. The inter-core communication ability is the key to the performance of the whole system. On-chip interconnection network is proposed to provide high bandwidth, low latency communication for future multi/many-core systems.The router is the key component of the on-chip interconnect network. The performance of the network is greatly determined by the design of router. This paper proposes a speculation mechanism, which guarantees that the speculative switch arbitration always agrees with the virtual channel allocation result. Thus, speculation efficiency is improved and the router traverse latency is decreased in both light and heavy traffic. Routing computation and buffer writing are executed in parallel, and the routing computation latency can be hidden. Comparing to the conventional5-stage router, the network latency can be decreased by10%～28%. Our speculation has higher operation frequency and less power and area overhead, and outperforms the existing speculation by4.4%.Topology determines the distribution of each node in the network and influences the network latency. The current integrated circuit technology limits the use of high dimension topologies. For the same network costs, we evaluate three topologies by simulation and synthesis. The results show2-D torus has the best performance. We also compare the crossbar with on-chip network. It shows when connecting8nodes, crossbar performs better than on-chip network and has much less costs. However, with nodes increasing, the performance of crossbar decreases rapidly.As the scale of the on-chip network grows, software-based simulation no longer meets the requirement of verification. In multi-FPGA verification platforms, the wires between FPGAs are not sufficient to map the network channels. In this paper, we design a serial transmission module to solve this problem. Using this module, we verify the on-chip network building block design by constructing a whole SoC. We also utilize the FPGA platform to evaluate two different on-chip network design for comparison.