The Design Of Slave Part In Digital Image Processing System

Field programmable gate array (FPGA) has developped rapidly in recent years, it has high development efficiency, low cost, simple technical maintenance, good reliability and other advantages, especially with the rapid development of the technology that based on IP core, embedded microprocessors,high-speed DSP algorithms in the form of the IP core embedded into the FPGA so that it can be more widely applied in the field of information and communication, automatic control, digital image processing. The thesis comes from the actual project of "Digital Image Processing System", the thesis develops a digital image processing system based on FPGA, which can achieve the capture and track of underwater moving targets. The system is divided into two parts:the master part and the slave part, the master part completes the control of the slave part and the acquisition and storage of image, the slave part completes the acquisition of image, and the implementation of image processing algorithms and the upload of image. This paper introduces the slave part in the system, it describes the overall system functions and design, the hardware and software design and implementation of the slave part.The slave part is designed according to the core device-FPGA. For hardware design, it uses LVDS high-speed data transfer interface, support64-bit image width; it uses RS-422interface to communicate with the master part; it uses DDR2memory module as the cache of image processing algorithms; it uses large-capacity data memory chips XCF128X as the configuration device to store the FPGA program flow. For software design, the implementation of image processing algorithms is the key, it uses the Xilinx EDK to achieve the acquisition and tracking algorithm, it includes the MicroBlaze soft processor, interrupt controller, serial communication, multi-port memory controller and other IP. In addition, in order to make the master part to capture and display the image successfully, it uses FIFO to generate the processed image data with the pixel sync, line and frame sync signals to transmit to the master part.After the design is completed, the whole digital image processing system is tested, the result shows that all the functions are realized, the image processing algorithms run properly, the master part is able to show the capture and track results accurately.