Research Of Mapping Methods For3D-Mesh-oriented CMP Networks On Chip

For a long time, processor researchers use super-pipelined、superscalar launch、out-of-order emission、dynamic branch prediction and other technologies to improve the calculation and processing capacity of the single-core chip. When the IC manufacturing process entered the era of Deep Sub-Micron, the designing complexity increased rapidly. The enhancement of the clock frequency has reached a bottleneck, and the chip’s line extension is greater than the gate extension which has become the major negative factor. All of these impacts caused that the performance of single-core processor has almost to an extreme. Therefore, the use of the network connection of highly parallel multi-processor array structure is the inevitable choice of a new generation of multi-core processors (CMP). With the improvement of the level of technology, especially in recent years, the rise of the silicon perforation technology, made drilling holes in the stacked silicon wafers to achieve inter-chip interconnect come true. Which has directly pushes the structure of network on chip into the3D era from the2D era.3D-chip network will package multiple wafer layers with three-dimensional into a single chip, this technology can shorten the distance between the processing core of the network> reduce power consumption、reduce extension, and improve reliability. Since we plan to design the suitable network for multi-core processors (CMP), we have to consider the node equality and the feasibility of implement.therefore the3D-MESH structure has become the mainstream choice of the CMP on-chip network. However, that how to fully use the on-chip network technology to improve the performance of CMP, is a big problem which need a further study. Currently, at home and abroad, researches based on the3D-chip network are rare, this article select the mapping algorithm to3D-MESH NOC as the major target study, and expect to make a new attempt for domestic CMP technology in3D on-chip network of basic research.Many factors can impact the communication performance of on-chip network, and one of the most important factors is the way of mapping tasks to the target network. And the choice of mapping method is complicated which is closely related to routing algorithm、switching strategy、the topology of the target network and many other technologies. However, there is no unified assessment model in the academic community currently. Therefore, this article give a detailed description of the essence of the mapping model firstly, then put forward a comprehensive on-chip network evaluation criteria which integrated a variety of evaluation parameters, and then we give the mapping models of all the evaluation criteria by analyzing the relations of domination between parameters in different models. This article put forward four requirements for the task of mapping CMP on-chip network as the following aspects:average delay in the network; the maximum delay under congestion conditions; total power consumption of the network; traffic balancing and how to avoid hot spots. Finally, we improved the Particle Swarm Optimization to solve the problem of multi-objective and discrete space in CMP on-chip network mapping algorithm.