Research And Implementation Of A Novel General Flow Measurement Chip

This thesis describes the architecture of a General Flow Measurement Chip and illustrates its realization from logic synthesis to layout based on0.35um CMOS process. This chip is achieved on the basis of the three projects, which is "Integrated Circuit Design of a Gas Volume Controller","Research on twelve-inch technology in Shandong Province", and "Test of the Huada EDA software" respectively. This chip is the improvement of the Gas Volume Controller, and can be used in the electricity meter, water meter, washing machines and other control areas. It can provide a reference for the construction of smart grid and smart home. Nowadays, intelligent terminals, IOT, and mobile internet have developed fast, and these emerging information and communication technology can be useful in the traditional control areas. Thus, people can easily use hand-held devices to remote control the electricity meter, water meter, refrigerator and other household facilities via mobile internet, making the life more convenient and comfortable. However, at present, the products of these areas are mainly composed of microcontrollers and discrete logic devices, which are lower integration, lower reliability, lower security, and higher power consumption. Therefore, the integration of this General Flow Measurement Chip provides an alternative solution for smart grid and other control areas.The main work in this thesis is illustrated as follows:1) Analyzed the architecture of this chip, proposed a novel design, given the application scenarios and adapted this chip into the Gas Volume Controller’s external interface for verification;2) Completed the logic synthesis, including given a detailed analysis about the design environment, design constraints and synthesis strategy; and given a gate-level netlist.3) Completed the physical implementation, including floorplan, placement, clock tree synthesis, route and DFM, and finish the layout design with time closure;4) Completed the Static timing analysis, given a detailed description about the principle and design steps, and achieved a timing closure verification;5) Finally, described the software and hardware co-verification method based on FPGA prototype, implemented the FPGA and ASIC verification platforms, illustrated the hardware circuit design and principles of the step-to-step debug techniques, and given the debug results.