Based On Cmos And Bicmos Process Research On Low Noise Amplifier And Mixer

According to the popularization of wireless communication equipment in recent years, radio frequency transceiver, which is the core of the wireless communication system, is racing toward broadband, low cost and miniaturization. Based on CMOS process60GHz short distance wireless communication technology, which has the advantages of ultra-wideband, ultra-high speed etc., is provided with the quite big attraction to consumer. Meanwhile, in order to decrease the cost of wireless communication equipment, engineers are trying to realize the RF transceiver monolithic integration by BiCMOS process. However, whether high-speed or low cost, low noise amplifier and mixer, which are the two important components of RF receiver, have the absolute influence to the performance of receiver. In this paper, the author designed a60GHz CMOS low noise amplifier, a2.4GHz single reconfigurable LNA, a2.4GHz differential LNA and mixer. The main contents of this paper are as follows:1. A low noise amplifier chip based on IBM90nm CMOS process is designed, the gain is more than18dB, the noise figure is about4.8dB, the consumption current is less than24mA;2. A2.4GHz single reconfigurable LNA based on IBM0.35um SiGe BiCMOS process is implemented, which provides three work modes:high gain mode, low gain mode and bypass mode. When the LNA is working in the high gain mode, the gain is more than18dB, NF is less than2dB, consumption current is less than3mA; When the LNA is working in the low gain mode, the gain is more than10dB, the NF is less than3dB, the consumption current is less than1.5mA; When the LNA is working in the bypass mode, the insertion loss is less than3dB, the NF is about3dB, which is similar to a switch. At the same time, the chip is provided with electrostatic discharge protection function.3. A2.4GHz differential LNA and mixer based on IBM0.35um SiGe BiCMOS process are designed, the gain more than27dB, the NF is less than3.5dB, the IIP3is more than-13dBm.The circuits designed by this paper have already achieved the expected design goal, but also have a certain research and reference value.