| With high-speed network development，the increase in the types of networkservices, requirements of network data bandwidth growed rapidly. At the same time, inorder to match the requirements of high-bandwidth network, copper access network wasgradually replaced by passive optical network（PON）. The OLT (Optical Line Ternimal)chip is the PON commander between access network and transmission network,responsible for the aggregation and distribution of upstream and downstream servicestream, as well as the bandwidth allocation of data stream. Its bandwidth of service datais the most important part in network performances. In order to meet the performancesof multi-PON data bandwidth, its internal cache management is essential. This thesispresents a cache management method based on the management of queue list and idleaddress in multi-PON network. This design achieves the multi-input random cachemanagement, at the same time achieving a large bandwidth, high cache utilization, lowcost and better versatility.Firstly this thesis introduces the cache management position and requirement inOLT chip. After analysis of function，performance and relevant technical requirements,and various technicals’ advantages and disadvantages, finally this thesis put forward tothe cache management solutions based on queue list management, table tennis memorytechnology, bitmap cache address management, and scheduling technology. Design inthis thesis meets8PON20Gbps bandwidth of ethernet data, the cache unit size is64bytes, using a single port SRAM and bitmap address management. This thesis meets therequirement of high-speed, large bandwidth, cost down, at the same time to meet theuplink and downlink general versatility. The final chapters are introduced the results ofsimulation and FPGA test of the cache management in OLT chip system.Design in this thesis is integrated into a OLT chip for a data path module, with10Gbps ethernet data flow in uplink and20Gbps ethernet data flow in downlink. |
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