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The Channelized Receiver System Based On Fpga Design

Posted on:2013-12-10Degree:MasterType:Thesis
Country:ChinaCandidate:X F ZangFull Text:PDF
GTID:2248330374486700Subject:Communication and Information System
Abstract/Summary:
Software defined radio is a hardware and software system which can be updatedand configured. SDR can replace certain analog hardware and enable the digital systemwork on higher frequency and be more flexible. Digital channelized receiver is animportant application of SDR in digital receiver system.This paper has realized the digital channelized receiver based on polyphase filtersand Fast Fourier Transform (FFT). The sampling rate of system is200Msps and theprocessing bandwidth is100MHz, the system can receive signals from32individualchannels and convert the Intermediate frequency signal to baseband. The sampling rateof output signal is3.125Msps and the bandwidth of each channel is3.125MHz. Thanksto the method of polyphase resolution, the system can obviously reduce the resourceconsumption compared to the traditional digital down conversion system.Firstly, this paper introduced the basic theory of digital sampling, digital downconversion and digital channelized receiver, then, it introduced the designing method ofNCO, FIR filter, delay and decimation unit, polyphase filter banks and FFT, then itfinished the programs and the simulation using Verilog HDL. Finally, it synthesized andmapped the system and run the system on the Xilinx FPGA hardware.This paper used MATLAB to finish the verification of the digital receiver’s model.Then it used ISE, MODELSIM and Synplify PRO to finish behavioral simulation andsynthesize, map, place and route. Finally it used the Xilinx developing board to verifythe hardware result.
Keywords/Search Tags:software defined radio, digital channelized receiver, polyphase filters, Fast Fourier Transform
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