Research And Implementation Of Network Shared Cache In The Chip

Along with the rapid development of internet and other data provision services, Optical Transport Network (OTN) is shifting towards the trend of high speed, high capacity, and greater coverage. It is a technology that is based on wave division multiplexing, providing larger particle profession, greater efficiency control, more diverse expenditure management, a complete and standardized system of technology, resulting in OTN becoming one of the mainstream optical technologies of the next generation.Most OTN internet chips have the base mechanism of store and forward. Because of the concept of multi-passaging in time division multiplexing, each passage often corresponds to different services. Each service space needs to be processed separately. The shared cache is a mechanism which enables the different passages to utilise the same storage unit, which reduces the amount of storage resource required, hence its price and power consumption.This thesis focuses on the design concepts of shared cache space of OTN internet chips. In contrary to the problem of the large amount of buffer required in them, the thesis designed and achieved the shared cache circuit by enforcing the concepts different passages sharing the same storage resource. The circuit design was also checked at the end.Initially this thesis thoroughly explains the concepts of the shared cache mechanism and related technologies; the management of linked lists, vacant address and the process of prefetching. It then describes operation process of shared cache, taking into consideration its reliability and achievability.Secondly it introduces the design of the application background and functional requirements of the shared cache chips, describing each chip function thoroughly, then providing their design and construction process.Finally it explains the validation method based on VMM, giving a detailed strategy using the SystemVerilog based on the conditions of the shared cache circuit, at last it performs the simulated testing of the designed shared cache circuit.