The Reliability Modeling And Simulation On Power Module Based On Embedded System Package

Embedding the power chip in polymer as a package helps the reduction of the size and cost, and the improvement of the function and performance. However, the mismatch of the thermal expansion coefficient will result in chip warping, cracking and other problems due to the thermal-mechanical stress. Hence, the reliability issue of the power chip becomes a major obstacle of the technology development. This thesis studies the reliability of the embedded power device packaging, and the contents and conclusions will be listed in the following paragraphs.Firstly, the static sub-structuring simulation methodology was proposed to model strip level warping of embedded die power package in ANSYS. The data from the parametric study showed that the thickness of chip and EMC had a great impact on warping in power device packaging process, while changing the prepreg Ez and EMC elastic modulus has no significantly effects. That is to say, if we change the chip thickness from0.1mm to0.4mm, the strip level warping would be reduced about66.98%when temperature rose from150℃to260℃or decreased from175℃to25℃. And the same case with EMC (epoxy mould component) the warping increases about4.56times when temperature rises from150℃to260℃, and4.53times when temperature decreases from175℃to25℃. Meanwhile, the same trends can be found in the internal structure of singular package by calculation results.Secondly, a three-dimensional finite element model of the embedded power device package is developed, and a life prediction based on Anand model is studied for thermal cycling temperature from-40℃to125℃and0℃to100℃. Through this simulation, we found that the corner joint fails and the cracks generated from its side of the PCB panel. By the parametric operation, we found that the life of solder joint increases with the height of solder. For example, the joint’s life increases about50%while the height was doubled. The height should be more than0.2mm at thermal cycling temperature from-40℃to125℃while a little bit more than0.05mm at the level from0℃to100℃.Finally, the input-D method is applied to test the reliability for power modulus with embedded die package under board-level drop test condition. According to the JEDEC standard, a three-dimensional finite element model for drop test of the power embedded die package structure is established, and the simulation results showed that the stress wave transmitted from the substrate bottom and then extended to the spot. Besides, the U1near the PCB panel got the maximum stress. In addition, the simulation also showed that a lower solder joint height had a higher reliability.