The Research Of Test Data Compression Method Based On Compatibility Analysis

Testing has become an essential part of Integrated Circuit (IC)implementation processes.With the manufacturing technology of ICprogressing, more and more Intellectual Property cores can be integrated on asingle chip. Thus, the number of test data for a single chip increases sharply,itexceeds the limits which test equipment performance allows, brings someserious challenges to the storage capacity, working frequency and bandwidthof Automatic Test Equipment, and results in higher test cost.At present,test data compression technique is an effective approach tosolve the problem of the great volume of test data. This dissertation proposestwo new test data compression schemes based on data block compatibility byanalyzing a variety of efficient test data compression methods. The contentsare as follows:Firstly, this dissertation introduces the background knowledge of testingand test data compression,and the problems of testing.Then,the previous workon test data compression is divided into three main categories: coding-based,linear-decompression-based, and broadcast-based schemes,and focuses onseveral classical methods about test data compression.Secondly,the analysis of the data block compatibility finds that most datablocks of the test data are incompatible just because of the very small part ofincompatible corresponding bits. In response to this situation, this dissertationproposes a novel test data compression technique using bit-transitioncompatibility, which puts these data blocks in a same group, uses the sameSelective Huffman codeword to indicate, and uses a dictionary encoding toindicate the bit transition positions in the data blocks. Therefore, it canenhance the frequency of the data blocks encoded by short code word andreduce the number of the data blocks not encoded, which provides asubstantial improvement in the compression ratio.At last,by analyzing test sets, we find a phenomenon called shakingphenomenon that affects the compression ratio, and we should updatereference data blocks continuously to reduce shaking times of the whole testsets to improve the compression rate further by taking example by ideas of virtual memorizer in Computer Operating Systems.This dissertation performs the related experiments based on several largercircuits of ISCAS-89benchmark circuit, and the test set is generated by theMintest Automatic Test Pattern generation tool. The experimental results showthat the two coding methods proposed in this dissertation, which based on theanalysis of the compatibility can effectively compress the test data and havegeneral applicability.