Research Of The Fault-tolerant Communication Components On Network-on-chip

The feature size of the electronic components in the shrinking to the nanometer level during the21th.So integrating a whole system in a single chip is possible. The emerge of the System on Chip(SoC) represents that the integrate circuit is transforming to the integrate system. However, SoC cannot satisfy the demand for parallel communication between the multi-cores in the chip because of the shared bus communication mechanism. And at the same time, the long bus will bring the problem of interconnect delay and huge power consumption. Therefore, in the1990s, researchers presented a new communication mechanism-Network on Chip(NoC). NoC adopt the idea of the internet to deliver data packets by several hops, it can solve a range of issues of shared bus.This dissertation introduces the development background of the NoC, and briefly introduces the reliability problems of the chip designing. And then introduces the research situation at home and abroad. At last, this dissertation research the fault-tolerant hardware in NoC:(1)the fault tolerant mechanism of the network on chip with the critical IP core strengthening. The fault of router in NoC will make the IP core connected with it cannot communicate with other IP cores, which affects the performance of the network on chip seriously. This dissertation presents a fault tolerance mechanism based on2D-mesh structure. This mechanism connects the resource network interface of the critical IP core and that of the neighbor IP core to strengthen the critical IP core. And at the same time the congestion mechanism is used to improve the efficiency of the communication of network on chip. Quartus Ⅱ software is used to verify the hardware in this dissertation, and OPNET software is used to test the fault tolerant mechanism.(2) Network on chip uses routers to transport the packets, so the routers’performance becomes the key factor which affect the delay and the throughput of the network, and at the same time the fault of the routers can also lead to data packet error. This dissertation presents a high-speed fault-tolerant router design for2D torus NoC topological structure. With the using of the bypass mechanism, the design in this dissertation make the packets across the router without any routing processes, and can make the router tolerate the hardware fault. The QuartusⅡ software is used to verify the hardware design, and the routing algorithm in this dissertation is compared with the typical fault-tolerant routing algorithm. The experiment results show that the added logic electric circuit can improve the performance obviously with a little of hardware resources.