H. 264 Video Coding Standard Entropy Coding Research

H.264is a source encode standard which offers excellent video compression efficiency and good net affinity. It can be used in many areas such as digital TV, video phone, video meeting, Internet video transmission and so on. The key technologies in H.264include intra prediction, inter prediction, data transform and quantization, entropy encode. Entropy encode is design to transform quantized blocks to bit streams. There are two entropy encode algorithms:Context-Based Adaptive Variable Length Coding (CAVLC) and Context-Based Adaptive Binary Arithmetic Coding (CABAC). CAVLC algorithm is design to encode residual blocks by using some LUTs based on context information, which has a high encode speed. The main features of CABAC algorithm are binary arithmetic coding and the adaptive update of probability state. These features lead to a high improvement of compression efficiency, but also the improvement of encode time.To CAVLC, this thesis presents a hardware framework which can bring a high encode speed and need less hardware resource:Design5parallel encode modules which can encode the5syntax elements at same time; Use arithmetic circuits instead of LUTs which can reduce the use of hardware resource; Design a six-staged pipeline structure to improve the speed of encoder.To CABAC, this thesis focuses on the improvement of binary arithmetic encode module structure:Use LUTs instead of binary floating point multiplier; To the choice of probability state, this thesis simplifies the probability-state-index calculation process; Design a three-staged pipeline structure to improve the speed of binary arithmetic encode module.In this thesis, Verilog HDL is used to write RTL code of the above hardware structures, ModelSim is used to simulate the function of modules and Design Compiler of Synopsys is used to compile the design based on TSMC0.13μm.The result of simulation and compile shows that the modules reach the goal:the max speed of CAVLC encoder is200MHz and the max speed of binary arithmetic encode module is500MHz.