Font Size: a A A

Based On The Low End Of The Memory Test Platform Of A/d Converter Test Plan Development And Implementation

Posted on:2013-09-20Degree:MasterType:Thesis
Country:ChinaCandidate:X SuoFull Text:PDF
GTID:2248330395450299Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
It is a big challenge to test advanced mixed signal devices, more advanced test equipments and more test time will be required. Verigy93000, Teradyne J750and Advantest T6series are the leading mixed-signal testers in the industry. These testers are very powerful but expensive. It will cost more than100USD per hour.To guarantee the performance of the mixed-signal SoC and save testing cost, a new mixed-signal test solution realized on low cost memory tester was researched in this thesis. Based on memory tester’s architecture, it is possible to implement multi site parallel test. Multi site parallel test can reduce test time effectively, and low cost memory testers are cheaper much more than mixed signal testers.In our test platform, an SRAM of the tester was used as waveform memory, with a high precision DAC to implement an arbitrarily waveform generator with directly digital synthesis technology. Another SRAM of the tester was used as waveform memory of capturing digital output from the ADC under test. A ramp pattern generated by the tester’s APG (Auto Pattern Generator) unit forced the DAC’s digital input, an analog ramp waveform was generated, and the ADC sampled the ramp waveform meanwhile. The ADC’s digital outputs were captured into SRAM of the tester. The static parameters including DNL (differential non linearity), INL (integral non linearity), gain error and offset error were worked out by processing the data of ADC’s output. An analog sine wave was generated forced the DAC’s digital inputs with a sine pattern, and the ADC sampled the sine waveform meanwhile. The spectrum of the sampled waveform was got by FFT conversion of ADC’s output data, and the dynamic parameters including SNR (signal noise ratio), THD (total harmonic distortion) and SINAD (signal to noise and distortion ratio) were worked out. Based on the new test platform we completed a10bits ADC test, and obtained static parameters test result:INL=0.93LSB, DNL=0.76LSB, Offset Error=0.74mV and Gain Error=22.87mV; dynamic parameters test result:SNR=59.82dB, SINAD=59.59dB, THD=-73.64dB and ENOB=9.606. After compare the test data between the new test solution and test bench, the new test platform was proved to meet the testing requirement.
Keywords/Search Tags:ADC, test, DNL, INL, SNR, FFT
PDF Full Text Request
Related items