0.35 Mu M High-pressure (14 V) Technology Platform To Improve Yield Improvement And Defects

With the rapid development of integrated circuits (IC), the integrity density is increasing and new requirements are demanded for design and process, including the high voltage IC (HVIC).This thesis investigates the issues, mechanisms, experiments and solutions for yield enhancement and defect reduction on the0.35μm HV14V process platform developed at the author’s company.Process optimization is carried out to increase product yield. The stability of low voltage PMOS (LVPMOS) drive current Ionp can be improved by reducing the LPCVD temperature from800to690℃in spacer oxide deposition. In such a lowered-temperature process, the diffusion of boron atoms introduced from LDD implant is minimized, therefore the control of the Lonp uniformity from wafer to wafer becomes better. The less-etch or over-etch issue can be solved using a by-time etch recipe with an APC table, which is a self-chosen etch recipe according to former oxide thickness for silicide etch process. The contact leakage fail resulting from weak inversion or non-inversion in N-type contacts is prevented by increasing the phosphorus implant energy from40to50keV.To eliminate certain type defects regularly occurred in some wafers, process optimization works have also been done. Sometimes there was a circular embossing defect on the wafer backside, which may result in backside discolor and front exposure defocus issues. A new recipe with a1s-reduced etch time for FEP wet etch can solve this problem, in which the over-etch of backside polysilicon can be avoided and the HF wet etch process has more margin. To avoid possible aluminum exposure at a wafer edge after chemical mechanical polishing (CMP) of inner dielectric, the steps at wafer edge areas can be lowered by skipping the edge cut during the via litho exposure. The over-polishing at the wafer edge is minimized due to the reduced polish rate. Before thick high density plasma (HDP) oxide deposition on an aluminum layer, a500A TEOS oxide layer inserted in between can effectively relax the mismatch stress between the two layers. As a result, bubble sometimes occurred in the mark area after the heating of HDP oxide can be completely eliminated. After the above process modification, the0.35μm HV process developed at the company is further optimized. The process margins for some products have been expanded, certain regularly occurred defects have been eliminated, and the product yield has been enhanced. Those optimized processes have been successfully employed in the production at the company.