Research On Key Technology In The Physical Design Of Muki-core Parallel Network Processor

Nowadays, the Internet has been developing rapidly. People have more and moredemand on the network data processing and transmiting. For the updating networkprotocol and faster and wider network bandwidth, a number of network packet processengines are integrated in the Network Processor, called Multi-core Network Processor.With the rapid development of IC industry, it has been entered into the ultra-deepsubmicron, nanometer era. In order to meet the demand of performance, power and cost,the physical design of chip becomes also more and more complex.Based on the overall structure of XDNP, the strcture characteristics of Multi-coreProcess Engine and On Chip Bus (MPE-OCB), and parallel work mechanism ofMulti-core Process Engine facing to Gigabit network data transmission are researchedin this thesis.According to data flow and strcture characteristics, physical designs ofMPE-OCB are achieved in both eASIC Nextreme90nm platform and SMIC CMOS0.13μm platform. eASIC Nextreme90nm platform and taped out successfully ineASIC Nextreme90nm platform, and the operating frequency is up to120MHz.Adopting the method of single-core XDPE flat physical design and MPE-OCBhierarchical physical design, hard core IP design of MPE-OCB is completed withSMIC CMOS0.13μm process, the operating frequency is more than200MHz.