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Design And Realization Of EMAC Module In HINOC Network

Posted on:2011-10-31Degree:MasterType:Thesis
Country:ChinaCandidate:Y L ChenFull Text:PDF
GTID:2248330395462580Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
HINOC (High performance Network Over Coax) bridges the last100meters from fiber node to home since fiber is widely deployed and used. HINOC is a home broad-band access network communicating over exiting coaxial cable. HINOC technology completely uses the cable of wired TV, only adding the devices of HM (HINOC Modem) and HB (HINOC Bridge) without changing the current wire line. HINOC provides high-speed and high-quality access for multi-services, such as voice, IPTV, SDTV/HDTV and data.Firstly, the features and current development of triple-network convergence are presented in this thesis, and then, the reasons of appearance, characteristics, advantages and development prospect of HINOC network are educed. Secondly, the design of HB/HM SoC chip which is the key deivce of HINOC is introduced, and the important effect of EMAC between FPGA and external EPHY is shown, simultaneously, the holistic design of EMAC module is particularly presented. And then a Top-Down method to design and realize the EMAC module on FPGA is presented in this thesis. The work process of sub modules designed in EMAC module are described, including Data Receiving Module, Data Transmitting Module, Controlling Module, MII Interface Manager Module and Register Module, and all these sub modules are designed by using State Machine and coded in Verilog HDL, every sub module is performed the timing simulation. Finally, the testbench is established, all sub modules are connected as a complete EMAC module to perform the functional and timing simulation by ISE10.1and ModelSim, and finally the whole EMAC module is validated in FPGA, and it is validated that the EMAC can be compliant with HINOC specification and IEEE802.3Standard. In this EMAC module, the processes of decoding and error-free reception are realized during frame receiving. During frame transmitting, the Preamble and SFD are inserted and the count of CRC is processed in the EMAC module. Moreover, a standard flow control mechanism is also included in this EMAC module in the mode of full duplex. The seamless and fast connection between FPGA and Fast Ethernet PHY chip is implemented in EMAC module. Finally, the correctness and practicability of EMAC module demonstrated in this article are successfully validated.
Keywords/Search Tags:HINOC, EMAC, data transmit/receive, flow control, timingsimulation
PDF Full Text Request
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