The Process Research Of Wafer Thinning And Backside Metal Deposition

This paper is based on the project of TI (CD)“Wafer Backside Process”, mainlyintroduce that grind wafer from725μm to100μm, and go through wet etch to enhancethe roughness of backside silicon, then deposit metal on the backside. The process canreduceR DS(on)and die thickness, improve heat loss and other aspect of chipperformance.In real life, the development of semiconductor technology mainly is reflected in thereduction of Critical Dimension. People focus on the CD improvement from90nm to60nm, even the breach on45nm,22nm, thus the semiconductor technology had comesinto the Nanometer times.With reducing of critical dimension, the more transistors per unit area, the morepowerful function chip will has, as a result of integration density increasing, heat willcentralize on the chip, so it’s become more important to keep chip’s good cooling statusto reduceR DS(on)and ultra-thin chip has become to another difficult and serioustechnology subject and demand to solve for a long time.Although，the effective thickness of device and contact wire in die should be5to10μm, to make sure Integrated Circuit working normally, a limited wafer thickness with20to30μm is needed, which is just a little part of the whole wafer thickness, theremaining is makes sure the intensity will be enough for manufacture, test, assemblyand transportation. When FEOL finished on the wafer, it will be a backside grindingprocess to meet the backside thickness requirement. Some special chip, such as PowerDevice, metal deposit will be needed after backside grinding to define metal contact,then die saw to independent chip and assembly it.In the following process, wafer need to meet the requirement of hear-stress to avoidbreak. Continual improvements, like equipment upgrade and excellent processintegration both FEOL and BEOL, which need to keep watching and reinforcing in thewhole process.The trend of final backside thickness will be reduced to thinner. When the waferthickness less than50μm, wafer would warp in certain degree and do not easy to break,even some special ultra-thin wafers would warp as you want, which would be used asflash and electric label.After solved the problem of thin wafer breakage, it will be a big challenge on backside metal etching and backside metal deposit.3main issues need to be conquered:1). Appropriate stickiness between wafer and metal to avoid them crack or peeling off;2). No obvious defect occurs when backside metal deposit process;3). Prevent backsideprocess to generate electric or reliability issue.The key point of this paper is that, according to the backside process and a mountof data which based on engineering experiments, which provides the solutions onprocess defects reduction and also reduces the cost and the time for mass production.