Study Of Netlist Generation Methmod For The VLSI Automatic Test Equipment Interface Board

The increasing difficulty of IC testing is along with the developing integrity. Modules inIC are hard to access. Test should be performed on functions and specifications of IC, so thatthe quality and reliability can be guaranteed. Therefore, testing and verification play a vitalrole in semiconductor industry.Generally speaking, the connections between the electronics ports are solided inschematic design phase. None of these connections can be swapped. However, functions andspecifications of channels in per-pin VLSI automatic testing equipment (ATE) are unique. Sothe swap can be made between these channels. With this special property, the netlist can bedesigned and optimized properly. Most PCB design softwares contain routing toolkit butwithout netlist generation toolkit. This thesis introduces mathematical tool in order to changethe artificial interface board design mode partly. The method introduced by this thesis canincrease the efficiency and reliability of IC testing with cost reduction. Few research reports onthis issue.Overall, this thesis is based on the analyse of per-pin VLSI automatic testing equipmentcharacterization and the limitation of conventional interface board design mode. It is found outthat netlist is the bottleneck of test interface board design. Firstly, the link is establishedbetween the netlist of interface board and weighted bipartible graph in graph theory. The objectof netlist generation is also brought up. Secondly, Hungarian algorithm is selected to resolvethe issue. The generation process of Hungarian tree and the creation/expanding process ofequality subgraph are deducted properly. The complexity of computing is also analyzed toensure the efficiency of the algorithm. Lastly, Euclid distance is chose as the edge weightedfunction from three classical type of distance.Some cases are studied to verify the netlist generation method introduced by this thesis.The speed of convergence and the accuracy of result are guaranteed by introduced the accuracyfactor p. because of the symmetry of the IC package and the interface board, it’s announceedthat breaking down the issue and utilizing the parallel computing technology are goodresolving policy. This netlist generation method is simple and efficient. It is beneficial to fastand high density routing on ATE interface board.