Research On The SRAM Structure In The Nanometer Process

The static random access memory (SRAM) is a key part of modern SoCs whose performance including power and stability is a key factor to the entire chip. As semiconductor technology scaling into the nanometer regime, the parameter fluctuation and leakage power are all growing, which making the design of SRAM face new problems in stability and power consumption.The power consumption and stability of the SRAM cell have been studied and analyzed deeply in this thesis by analyzing the problem of power and stability which is faced in designing nanometer process IC. Here we introduce the mechanisms including power gates, transistors stacking, body bias effect and FinFET transistors to reduce power consumption and then compare the results. Also, the indicator called static noise margin which is used to analysis the stability of the SRAM structure is introduced in this thesis. The dynamic power mechanism and several SRAM cell structures which have a better stability are introduced in this thesis. The sources of dynamic power and static power consumption of the SRAM are analyzed and the results of simulation analysis are showed. We also analyze the source of noise in the structure, introduce the Monte Carlo analysis, and analyze the noise read static noise margin of SRAM structure by executing2000Monte Carlo simulation analysis.By studying the sources of power consumption and noise, we redesign the structure and propose a new8-transistor SRAM cell structure. Then we describe the composition of the new structure in detail and analyze the power consumption and noise sources. Ar last, we compare the performance of the new8T unit and the standard6-transistor SRAM cell.The methods of gated power, mechanism of subthreshold voltage, mechanism of dynamic power and mechanism of using FinFET transistor are adopted to enhance the the new8T structure’s performance of power consumption and stability. The results are compared in the thesis.