Design And Implementation Of SoC Debug And Trace System

With the fast development of SoC technology，the complexity of SoC haveoutgrowth traditional debugging methodology. A typical SoC now contains multipleprocessors of different types, several different buses, loads of embedded software, anda multitude of discrete signals. With only a fraction of the internal signals visible at thechip I/O, there is very little visibility into what is going on inside the chip. Without apowerfull debug system, both hardware and software design will become very difficultwhen use a SoC to develop an embedded system.This article research the requirements of SoC debug and trace system, finish thedesign and verification of debug and trace system in a baseband SoC chip. This articlefirst introduced the principles of JTAG technology, including JTAG interface and thedebugging process by using JTAG. Then describe ARM coresight component in detail.This article realizes a debug system by combine JTAG and coresight technology, whichcan access the IP with either AHB/APB interface or JTAG interface. The simulationresults are given in appropriate chapter.SoC trace system design is another point of this article. This article analyzes theissue about SoC driven by multiple asynchronous clocks and give relevant solution tohandling different problem. A trace system is developed, which matches the SoCmulti-core trace requirements.As different IP core has different message format, thisarticle refers a common trace interface and give a detailed trace interface for powercontrol unit. To improve trace pin utilization, an arbiter is designed to managemulti-core trace interfaces.The principle of power dissipation，the sources of dynamic and static powerdissipation are analyzed as well. The strategies, clock gating and power domainpartition, are applied to the debug and trace system.