Research And Implementation Of High Performance Switching Unit Input Interface Module In Space Station

With the development of space technology, space station needs to deal with the rapid growth of transferring its transactions. It puts forward the internal bus communications systems increasingly high requirements, and designing suitable application environment for the space station’s network technology is becoming an important issue. Because of great and long-term technology accumulation, the traditional Ethernet network has become the mainstream of the LAN transmission technology. The traditional Ethernet lacks of communicational real-time characteristics and certainty guarantees, although in recent years the gradual rising real-time Ethernet can give certain guarantees in real-time and certainty, there are still no unified standards and suffers of deficiencies of unclear development direction. The AFDX (air full-duplex Ethernet) can set up business easily and ensure the real-time characteristics and certainty of communications. On this basis, we propose a traditional switched Ethernet and AFDX combined networking program for the space station.According to the undertaking research project in laboratory-"Research and Implementation of High-Performance Switch in Space Station," the main task is to design a full-duplex, high-performance non-blocking switch to accommodate the space station application environment. Based on the project, this thesis mainly elaborates the design and implementation of forwarding table, filtering, policing and the bus module of the switch. The forwarding table module is mainly to solve the problem of finding the output ports of Ethernet frame as well as the relevant parameters of the virtual link of AFDX frame. Filter policing module is to ensure the legitimacy of the data frame length, as well as the bandwidth of the virtual link of AFDX frame. Bus module is responsible for moving data from the input port buffer to the output port buffer. The code of all the modules compiled in Verilog HDL. In Xilinx ISE development environment, using the simulation tool ModelSim SE, the timing simulation of all the modules have been carried out. The simulation results verify the correctness of each module. Thus, the work of designing and the implementation of the FPGA are completed.