A Design Of Dual-output LDO Ic With Delay Power-on Reset

In recent years, with the development of portable electronic products, especiallythe rapid development of the battery powered portable electronic products，powermanagement IC put forward to higher request. The LDO linear regulators, as portableelectronic products, have been widely applied with high efficiency, simple and reliablecircuit structure and the small chip occupy area. LDO continuously improve theperformance to prolong the life of battery, effectively reduce power consumption. Itrequires higher efficiency, more functions, lower dropout voltage and lower quiescentcurrent.This paper introduces a dual-output low dropout linear voltage regulator whichmanufactured with XB060.6um BICMOS double well process in XFAB. The deviceinput supply voltage range from2.7V to6V, maximum output voltage is3.3V andmaximum output current up to3A. It only takes350mV typical drop-out voltage under1A load current situation. The smallest quiescent current of device is200uA. LDOChip integrated open drain power-on reset circuit block with200ms delay. It isindependent enable function for latter stage of DSP circuit. During chip design, outputpower-MOS add a rapid feedback circuit in former stage drive circuit block whichfaster the system response when big change happened in load. At the same time, chipalso has over-current protection and thermal protection function, which increase thereliability of system.The pivot of this paper is a dual-output LDO. Firstly it deep elaborated LDOlinear regulator structure and working principle, and then described the basis functionof each module circuit and point out key and difficulties. The method greatly shortensthe design period with line process. During the layout design, author full used XL toolto justify the Place&Route that reduced the waste of layout area and unnecessaryrework and accelerated the process of the design. The device used double guard-ring asisolation structure to reduce the noise; design the layout block for fuse trimming toreserve the later change space for reference voltage module and resistance sampling module which improved the reference voltage accuracy. The layout adopted a newmetal wiring layer punching method which simple the layout design. Finally, based onlayout characteristic of dual output voltage, it can be changed into another chip designby replace only one mask of METAL1.which greatly reduced the project cost.The design passed validation and test process by real chip. Some parameter evensuperior than forecast such as IOUT. The product has been handed over to customer.