Design And Implementation Of Testing Adapater Based On Embedded PC And CPLD

Embedded technology accompanied with the appearance and development of microprocessor.Meanwhile it integrated with the computer,microelectronics,network and communication technology closely.In the21st century,high-performance embedded systems hardware cores refer to32bit Alpha/ARM/PowerPC/MIPS/x86architecture SoC.These hardware platforms have powerful instruction(RISC or CISC) processing ability and abundant sources on chips.They can support complex OS,such as Linux,Vxworks,iOS and Android.Linux has good performance,and it’s very popular in both domestic and international programmers.It can be installed in smartphones, tablets, routers, desktops, mainframes, supercomputers and other devices. FPGA and CPLD are mainly used in data acquisition, interface logic, the field of high performance digital signal processing,especially in the mixed level enrvironment.Traditiorial voltage level converting method makes the circuit complex. The use of FPGA/CPLD which supports multi-voltage level can greatly simplify the design.This paper is about the design and implementation of testing adapter.It’s hardbare is based on x86architecture embedded PC and CPLD,and it’s software is based on Linux OS.It receives testing command from testing platform via RS232serial port,then tests the DIM and BIM according to the testing command.Embedded PC controls the CPLD via GPIO port,using SPI interface sequence.This method controls the sequence of CPLD’s I/O port which can provides the work sequence of UUT.Embedded PC controls UUT’s work pattern via reading and writing dual RAM of UUT.Testing platform communicates with UUT via related bus,then records the results in time.