Design Of An Improved Structure For Fast Locking PLL

With the development of microelectronics technology, phase locked loop (PLL) hasbecame the core part of modern communication systems. As the typical sort of mixedanalog-digital PLL，Charge-pump phase locked loop (CP-PLL) has became the mostwidely used PLL because of its characteristics of high-speed, low power consumption, lowjitter and so on. In high-speed circuits, almost all PLLs require fast locked. But theperformance indexes such as lock time, bandwidth, phase noise, power consumption, etcare conflicting. Therefore，it is essential to study how to faster lock.With the improvement of data transfer rate, PLL with shorter lock time is needed tomeet the demand of modern communication systems. Based on the improvement of thetraditional CP-PLL circuit, this paper proposed a new PLL structure, which can effectivelyreduce the lock time. In the theory of traditional CP-PLL, the way to reduce the lock timeis to widen the bandwidth by increasing the CP current. But power consumption and phasenoise are increased while reducing the lock time, even an over large bandwidth may resultin the loss of lock. To solve the problems encountered in the traditional CP-PLL, a push-incharge pump circuit is introduced in the traditional PLL. The impact of increasing the CPcurrent through the traditional way is weakened while speeding up the lock.First，the paper begins with the basic theory of PLL. Based on the understanding ofevery module, one mathematical module is set up. Second, According to the transferfunction, we can calculate the loop parameters under conditions that satisfy the phasemargin and bandwidth. Third, one improved structure for fast locking CP-PLL wasproposed after introducing the fast lock theory. Finally, the simulation results were givenand analysized.The design is based on the X-FAB0.35μ mCMOS process and the simulation tool isCadence. The results of simulation show that with a3V power supply, the output signal frequency is640MHz when the input reference signal frequency is20MHz，and the locktime of CP-PLL with the improved structure is3.3μ s.Compared with the traditional PLL，the lock time is reduced by35.3%,which has met the design requirements.