12bit 100MSPS ADC Clock Generator 1.8V CMOS-based Process

With the development of digital signal processing technology, and the increasing demand for precision and speed of analog-to-digital converters, high speed and high precision analog to digital converters have become the hot researches. As the clock jitter generating aperture effect can directly affect the accuracy and speed of the analog-to-digital converter (ADC), it’s significant to design clock generator circuit for analog to digital converter system.According to the request of the ADC clock, this thesis makes the design about the clock generator from the system level, circuit level and layout level.Firstly, the clock jitter requirement of the12bit100MSPS ADC system was identified. And then, based on the related theory of the clock generator circuit, this paper chose the clock generator design based on the phase-locked loop (PLL).Secondly, after the details study of the principle about the phase locked loop, the linear model of the phase-locked loop was established. According the deep researches in the non ideal effect about the charge pump phase-locked loop, the block of Third-Order Charge Pump PLL was chose to be the main circuit of the clock generator.Thirdly, after learning about the details of the circuits in the charge pump phase locked loop and the0.18μm mixed-signal CMOS process, the circuit designs about the phase frequency detector, charge pump, loop filter, voltage controlled oscillator and frequency divider were completely finished. The simulation results of the clock generator show that, the rms value of the absolute jitter is3.71ps, and the locking time of the PLL is about15μs, with the1.8V supply voltage and8mW power consumption, at the nominal template and process corner. Basically the simulation results meet the design specifications.According to the layout design rules, and the requirements about matching and noise in the PLL, the layout of the entire clock generator was completed. And the core circuit layout area is820μm×330μm.