| The simplest and most effective way to transmit data was ever to directlyconnect the coresponding input and output between chips, however, this willdramaticly increase the pins, on the other hand, the technology of package did notdevelop in the same pace in the past years. All of that come to the widely use of theinterface circuits in high speed data transmission system—the high speedSerializer/DeSerializer circuits, which become a more and more important part in ICdesign.The Serializer/DeSerializer circuit proposed in this dissertation is under theSMIC0.18μm process, with1.8V supply. The Serializer is integrated with8inputsof data which are all in150Mbps of data rate, and with an output for differentialserialized data in1.2Gbps of data rate. The DeSerializer receive a series ofserialized data which are later transferred to8parallel data in150Mbps of data rate.The Serializer/DeSerializer circuit in this dissertation includes three parts, the PhaseLocked Loop(PLL), Serializer and DeSerializer. The PLL in this system is used tomultiply the frequency of the reference clock and to supply a clock signal which isrequired in Serializer, the Serializer has the function of serializing the originalparallel data, while the Deserializer retrieve the paralleled data from the single dataflow. The key point in PLL design pays more attention to low jitter aspect, anadapted differential output charge pump architecture which is in conjunction with aCMFB circuit is used, and the ripple of the control voltage of the Voltage ControlledOscillator(VCO) is constrained in a relative low level, which makes the clock signalof output of PLL and the output data of Serializer have wide-open eye diagram,while the Serializer/Deserializer considers more on deburring, which achieves thetarget in taking an adapted delay lock data selector circuit.The design of layout is complished after the circuit design that based on somecertain requirments, the total area of this design is500μm×490μm. After LPE andpost simulation, the peak-to-peak jitter of the data output of the Serializer is40ps,while the peak-to-peak jitter of the PLL in this design is25ps, the performance ofthis system complies with the requirements. |
