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Research On Static Instruction Mapping Algorithm Of Edge Architecture

Posted on:2013-03-22Degree:MasterType:Thesis
Country:ChinaCandidate:W T WangFull Text:PDF
GTID:2268330392968727Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Along with the development of modern semiconductor industry, and the levelof integration of the chip, computer architecture design tends to divide processorinto tiles. The huge demand of processor performance drive the architecter to fullyexploit the program’s ILP. Under these background,EDGE (Explicit Data GraphExecution) architecture is proposed.Atomic execution, static placement dynamicissue is the characteristics of EDGE. Subdivided structure of EDGE need a kind ofmechanism to map instructions to the hardware, thus how to design the mappingmethod to achieve optimal performance for EDGE architecture is of greatsignificance.This paper summarizes the advantages and disadvantages of the existingscheduling algorithm and analyzes all the factors that affect the performance ofEDGE.Based on the principle that increasing bypass on node can reduce the amountof communication,this paper put forward and realized a Dependenece-Firstscheduling algorithm, namely DF algorithm. We evaluated and improved the DFalgorithm.The test results show that DF scheduling algorithm at most achieved13%higher performance than the existing best scheduling algorithm while on averagethis ratio become2%.This result show that DF algorithm can speed up applicationprogram’s execution.By analysising the complexity of the algorithm we found thatboth DF and SPS algorithm have the complexity of O (i2).At the end of this paper,we compare the performance of DF algorithm whenusing different hardfware.We doubled the bandwidth of bypass and network whileusing the same DF algorithm. and we discussed how the hardware affectes the DFalgorithm based on the result.By exploring the experiment’s data,we found that thebandwidth of bypass and network do affect the effectiveness DF algorithm.And weconcluded that the bottleneck of performance is the bypasswidth of TRIPSprocessor comparing with the network bandwidth.We achieved extra10%improvement by double the bypasswidth when using the same binary which DFalgorithm produced..
Keywords/Search Tags:EDGE, static mapping, TRIPS, hyperblock, instruction scheduling
PDF Full Text Request
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