Design And Implementation Of Floating Arithmetic Unit In FT-Matrix DSP

Digital Signal Processor is one of key component of the signal processing system,design of DSP for wireless communication base station will promote development,production and application of Chinese mobile communication infrastructure equipment.YHFT-Matrix is a high performance32bit DSP designed by National University ofDefense Technology (NUDT), which is mainly used for the application of wirelesscommunication base station of LTE.In order to research and design a high performance arithmetic floating-point unitfor LTE, the architectures of advanced DSPs for LTE were studied in this thesis.Furthermore, the kernel algorithms of LTE was analyzed and mapped into VLSIimplementation. The architecture of floating-point arithmetic unit includes16isomorphic operating units. Each operating unit contains a floating-point arithmetic partsupporting floating-point arithmetic operations of double-precision and single-precision.This thesis analyzes the basic algorithm for floating-point adder, compares severalmethods as the basis. Compound adder leading0/1judgment of the logic design ideasand methods are referenced to research and design the components of high-performancefloating-point arithmetic unit by using an improved single-path floating-point adderstructure. Pipeline station at detailed design stage is divided, and resources between thevarious floating-point instructions are reused. At last, the key components of thefloating-point arithmetic unit is studied and implemented, and low power controlmethod on the pipeline is studied by adding the station effective signal.Netlist’s function is simulated and verificated at gate level netlist and anti-markeddelay gate level on the implementation of the floating-point arithmetic unit, and netlistant-marked delay simulation and verification of typical LTE algorithms such as FFT arefinished at system level, gate level netlist and gate level. The coverage analysis ofverification work is also given. We synthesized unit of the design in TSMC65nmCMOS technology by using Design Complier of Synopsys, and the result shows that itsfrequency can reach500MHz, the power is5.45mW and the area is44887.68um2. Aftertapeout, chip board-level test and functional tests of typical LTE algorithms such as FFThave been done. The results show that the design requirement of500MHz is achived.