The Research And Design Of EDMA Interface In High-performance DSP YHFT-QMBase

LTE, HD video and other stream applications need more and more higher computingperformance of DSP because of their data processing density. In order to meet the requirement,vector and parallel, muti-core and other advanced processor technology are being widely used byhigh performance DSPs, and they will have become the trends for follow decades.Now high performance DSPs with abundant peripherals commonly employ EDMAcomponent to transact larger data between memories and peripherals. Because the performanceof EDMA affects data communication bandwidth and capability of data caculating efficiency ofDSP chips, some particular data transformation interfaces of EDMA for various peripherals mustbe designed to meet the needs of bandwidth of the data transferring and fulfill high performanceof data processing of DSP.YHFT-QMBase is a high-performance muti-core DSP chip for software defined radio basestation. It integrates4symmetrical DSP cores named YHFT-Matrix. YHFT-Matrix had beendeveloped by the National University of Defense Technology who has its independentintellectual property. According to the design requirements of YHFT-QMBase, the interface ofEDMA is studied and designed for YHFT-Matrix, and three private interface, vector reorderbuffer(VRB), AXI protocol conversion interface and Qlink affairs conversion interface, areproposed and implemented.The single core of YHFT-QMBase is based on muti-width SIMD technology and integrated16vector processing units and high bandwidth vector memory(VM). Data bandwitdh betweenVM and EDMA is wasted because of their bandwidth difference and increases the vectormemory access conflicts violently. In order to reduce the frequency of accessing VM and VM’saccessing conflicts to improve the efficiency of vector operations, according to the localityprinciple of EDMA accessing to the VM, VRB is designed between VM and EDMA for cachingthe continuous data.YHFT-QMBase has integrated an AXI protocol peripheral on chip. In order to realize thecommunication between the DSP core and the peripheral, the AXI protocol conversion interfaceis designed for EDMA. The conversion interface carries out the data package and unpackfunctions and signals transmission in asynchronously clock and solve the problem of reliabledata transmission between AXI peripheral and DSP core with different bus width and clockfrequency.Finally Qlink affairs conversion interface for Qlink device of YHFT-QMBase is designed inEDMA to achieve the data transfer among the VM of the four DSP cores in YHFT-QMBase.The interface reduce and hide the data transmission delay by the techniques of2-dimensionaldata transfer, reading data prefetch and writing data cache.Now YHFT-QMBase has been successfully tape out. Logic verification and chip test haveshown that the functions of the EDMA interface mentioned above are correct. VRB can reduce 92%conflicts when EDMA and VPU access VM simultaneously. The AXI protocolconversion interface can communicate with DSP core smoothly when RapidIO peripheral worksat the rate as high as3.125Gbps. The qlink affair conversion interface can decrease an average of186cycles of transaction switching delay.